Nicholas Oskiper

Overview

The Smart Walker project is an ongoing capstone initiative focused on developing a sensor-integrated mobility aid that enhances user safety, independence, and health monitoring. Unlike conventional walkers, this design combines embedded sensing, obstacle detection, fall prevention, and real-time biometric tracking into a single assistive device. Built using Arduino Nano 33 BLE, LiDAR, force and heart-rate sensors, and motorized wheel control, the system provides continuous feedback to both users and caregivers through haptic, visual, and digital interfaces.

The design will begin in the Spring 2026 semester with a team of 5 other students.

Objective

To design and prototype a smart, autonomous walker that:

• Detects obstacles and adapts to terrain using LiDAR and ultrasonic sensors.
• Monitors user vitals (heart rate, oxygen saturation, grip force, posture).
• Detects falls or loss of balance through motion sensors and magnetic safety straps.
• Tracks steps, distance, and activity levels using rotary encoders.
• Provides emergency alerts, auto-braking, and live data to caregivers via a Bluetooth interface.

The goal is a modular, human-centered assistive system that bridges robotics, biomedical sensing, and embedded control.

Tools & Technologies

Hardware: Arduino Nano 33 BLE Sense (x2), Pololu 37D Gearmotor + Encoder, Cytron MD30C Motor Driver, MAX30102 Heart Rate Sensor, FSR402 Force Sensors, HC-SR04 Ultrasonic Sensors & TFMini-S LiDAR, Piezo buzzer, RGB LEDs, vibration motor, magnetic reed switch strap

Software: Arduino IDE (C/C++), MATLAB (for testing), CAD (SolidWorks), Fusion 360 (3D modeling)

Build Materials: PVC framing, 3D-printed joints, weatherproof enclosures

Design Domains: Embedded Systems, Mechatronics, Human-Computer Interaction, Health Tech

Process

Physical Build

• Designed a PVC frame for modularity, wire routing, and balance.
• Integrated 3D-printed mounting brackets, control box, and handlebar enclosures.
• Power system includes a dual-voltage setup: 12V supply for motors/actuators, 3.3V and 5V rails for sensors via a buck converter.

Handlebar Subsystem

• Acts as the primary user interface and health monitor.
• Heart-rate (MAX30102) and force (FSR402) sensors are embedded within grips to monitor exertion and stability.
• RGB LED and haptic driver (DRV2605L) provide feedback on system status (e.g., obstacles, falls, or irregular vitals).
• Side-squeeze button allows the user to acknowledge alerts or silence false fall detections.
• Data is processed and transmitted via BLE to a caregiver dashboard.

Wheel & Mobility System

• Dual-motor design using Pololu 37D gearmotors with encoders for real-time distance and speed measurement.
• Speed regulated through PWM signals and MD30C motor driver.
• Torque requirement derived via mechanical modeling (≈1.5 N·m per motor) for user support up to 100 kg.
• Emergency braking uses regenerative deceleration—motor coils shorted to dissipate kinetic energy safely.
• Encoders track wheel rotation, converting distance into step count metrics for health monitoring.

Fall Detection & Safety Subsystem

• Magnetic safety strap operates like a treadmill key: disconnecting triggers an emergency stop.
• Onboard IMU (LSM9DS1) in the handlebar confirms abnormal acceleration or tilt patterns.
• Multi-stage fall logic: Free fall (acc < 0.5 g for > 250 ms), Impact spike (acc > 2.5 g), Posture settle (> 45° tilt for > 0.5 s), Strap disconnect confirmation
• Upon detection: triggers braking, piezo alarm, red LED flash, and caregiver notification.

Vision & Environmental Awareness

• LiDAR (TFMini-S) for precise forward obstacle detection (0.1–12 m range).
• Ultrasonic sensors (HC-SR04) provide peripheral awareness for side and rear obstacles.
• Real-time feedback loop between LiDAR/sonar readings and motor control logic for automatic braking or avoidance.
• Depth vision expansion planned using a 3D point cloud and RANSAC algorithm to refine fall detection and terrain mapping.

Software & User Interface

• Embedded Firmware (Arduino): Handles sensor fusion, motor logic, braking control, and alert generation.
• Desktop Dashboard: Displays real-time metrics such as heart rate, oxygen saturation, step count and walking distance, posture stability, obstacle proximity alerts and event history
• Connectivity via Bluetooth or USB, with stored logs for trend analysis and caregiver access.

Results (In Progress)

• Only planning has been done so far.

Challenges & Insights

• Integrating multiple MCUs and ensuring synchronized data flow requires careful I²C bus management.
• Noise isolation between high-current motors and sensor lines proves essential to maintain reliable readings.
• Designing for elderly ergonomics introduces trade-offs between sensitivity and comfort (e.g., vibration intensity, grip force thresholds).
• Safety redundancy: magnetic strap + IMU + vision cross-verification for zero false negatives in fall detection.

Future Improvements

• Integrate GPS and cloud connectivity for caregiver tracking.
• Add AI-based gait analysis and terrain adaptation algorithms.
• Develop mobile app companion for caregivers and family members.
• Pursue clinical testing and certification pathways (FDA Class I device).

Key Takeaways

• Demonstrates cross-disciplinary expertise spanning embedded electronics, mechatronic control, biomedical sensing, and UX design.
• Applies system-level engineering principles to a real-world healthcare mobility challenge.
• Strengthens proficiency in sensor fusion, motor control, and human-centered design.
• Embodies engineering for social impact — combining technology and empathy for accessibility.

Overview

I designed and implemented a 16-bit RISC-V–style processor entirely in SystemVerilog, culminating in a fully functioning CPU capable of executing branch instructions and signed arithmetic. The processor was built incrementally—from arithmetic logic to instruction flow—validated through simulation and real hardware testing on the TUL PYNQ FPGA board. The project demonstrates end-to-end understanding of how digital logic, hardware description languages, and computer architecture integrate to form a working processor.

Objective

Develop a modular, synthesizable processor that:

• Performs arithmetic and logic operations with overflow handling.
• Supports register-based data storage and memory read/write cycles.
• Implements an instruction decoder and program counter for sequential instruction flow.
• Executes branching and signed arithmetic operations autonomously.
• Verifies every stage via testbenches, simulation, and FPGA hardware testing.

Tools & Technologies

Hardware: TUL PYNQ FPGA Board, onboard LEDs & SSD

Software: SystemVerilog / Vivado / VIO Dashboard

Concepts: Digital Logic Design | Datapath Architecture | ALU Construction | Memory Mapping | Control Signal Decoding | Branching Mechanisms | Overflow Detection | Hardware Simulation and Verification

Process

16-Bit Adder – Arithmetic Foundation

• Designed a 16-bit ripple-carry adder handling overflow conditions.
• Verified correctness with SystemVerilog testbench simulations and FPGA LEDs.
• Gained practical insight into hexadecimal arithmetic and hardware overflow detection, building the first arithmetic block for the processor.

ALU Implementation – Core Processing

• Expanded the adder into a full Arithmetic Logic Unit (ALU) with selectable operations.
• Implemented a selector input to toggle between addition, subtraction, AND, OR, XOR, and comparison.
• Hardware testing validated real-time logic operations on the PYNQ board, demonstrating the ALU's role as the processor's computational core.

Register File – Memory Interface

• Built a Register File module integrating multiple registers with read/write ports.
• Connected the ALU through a multiplexer and a top-level module to simulate read/write operations.
• Observed efficient data storage and retrieval—a crucial step toward a functional CPU datapath.

Data Memory Integration

• Combined ALU and Register File modules with a new Data Memory component.
• Implemented load/store capability to pass data between registers and memory.
• Verified memory transactions on hardware, confirming correct operation of the datapath's memory stage.

Instruction Decoder – Control Logic

• Created an Instruction Decoder to translate opcodes into control signals.
• Supported arithmetic, logic, shift, load/store, and branch operations.
• Incorporated a debounce circuit to stabilize input switches during testing.
• Used VIO Dashboard for input/output verification, confirming proper instruction-to-control mapping.

Program Counter & Instruction Memory – Sequential Execution

• Added Instruction Memory and a Program Counter (PC) to automate instruction fetching.
• Loaded machine code into a distributed ROM, executing a sequence of RISC-V instructions step-by-step.
• Implemented control buttons to advance instructions and reset the system for testing.
• Verified correct instruction flow and execution through VIO and LED feedback.

Branching & Signed Arithmetic – Processor Completion

• Enhanced the PC to support conditional branching and signed operations.
• Modified the decoder to sign-extend immediate fields for negative values.
• Executed an assembly program performing signed multiplication, displaying output on the SSD.
• Achieved a fully functional processor with branching capability, completing the CPU design cycle.

Results

• Fully operational 16-bit processor verified through simulation and hardware execution.
• Accurate handling of arithmetic, logic, memory access, instruction decoding, and branching.
• Demonstrated complete instruction flow from fetch → decode → execute → memory → write-back.
• Reinforced understanding of how digital logic integrates into CPU architecture.

Challenges & Insights

• Managing timing synchronization between modules required iterative clock testing.
• Overflow handling in signed arithmetic exposed the importance of bit-width planning.
• Integration revealed how control logic complexity scales rapidly as features accumulate.
• Debugging with testbenches and VIO visualization proved invaluable for hardware-software co-design.

Future Improvements

• Expand to a 32-bit RISC-V implementation with pipelining stages.
• Introduce hazard detection and branch prediction units.
• Implement cache memory for performance optimization.
• Add UART I/O for serial communication and real-time debugging.

Key Takeaways

• Built an entire CPU datapath from primitive components.
• Mastered SystemVerilog hardware design flow from simulation to FPGA deployment.
• Developed strong proficiency in modular digital systems, control logic, and embedded debugging.
• Gained hands-on experience that bridges computer architecture theory and physical implementation.

Overview

Stride-Guide is a sub-$75 assistive device that empowers visually impaired users to detect and identify obstacles in real time. It combines a Raspberry Pi 4 running YOLOv3 deep-learning object detection with an Arduino-controlled ultrasonic proximity sensor. The system uses a dual feedback approach: the Raspberry Pi provides spoken audio announcements identifying detected objects through headphones or a small speaker, while the Arduino produces proximity-based beeping alerts (faster beeping indicates closer obstacles). This combination gives users independence, mobility, and confidence at a fraction of the cost of commercial smart canes.

Objective

Create a low-cost, hands-free assistive tool that:

• Detects and classifies real-world objects using YOLOv3 on a Raspberry Pi 4.
• Measures obstacle proximity with an Arduino-controlled ultrasonic sensor (HC-SR04).
• Delivers dual audio feedback: spoken object identification via text-to-speech from the Raspberry Pi, and distance-based beeping alerts from the Arduino (faster beeping as obstacles get closer).
• Operates on compact, easily sourced components for under $75 total cost.

Tools & Technologies

Hardware: Raspberry Pi 4 Model B (1 GB), Arduino Uno, Pi Camera v2, HC-SR04 Ultrasonic Sensor, Mini speaker/earpiece, Custom 3D-printed frame + mounts

Software & Frameworks: YOLOv3 (Darknet + OpenCV DNN) pretrained on COCO dataset, Python 3, OpenCV 4.x, NumPy, pyttsx3 (text-to-speech), Arduino C/C++ with NewPing library, Serial UART communication between Arduino and Pi

Design Tools: SolidWorks / Fusion 360 for enclosure and component layout

Process

System Architecture

• Raspberry Pi 4 performs real-time image capture, YOLOv3 inference, and spoken object identification.
• Arduino Uno continuously reads the ultrasonic sensor to measure object distance and controls beeping frequency.
• The Arduino independently produces beeping alerts—faster beeping indicates closer obstacles.
• The Pi announces detected object classes through text-to-speech, complementing the Arduino's distance alerts.

Object Detection Pipeline (YOLOv3)

• Loaded pretrained yolov3.cfg and yolov3.weights through OpenCV's DNN module.
• Frames resized to 416×416 and converted to blobs for network input.
• Performed forward propagation to obtain bounding boxes, class IDs, and confidence scores (>0.5).
• Used COCO label map to identify and verbalize recognized objects.
• Optimized frame rate (~10 FPS) using Pi-specific GPU acceleration and reduced image size.

Ultrasonic Distance Detection (Arduino)

• HC-SR04 emits ultrasonic pulses; echo time converts to distance (cm).
• Arduino controls beeping frequency based on measured distance—closer obstacles trigger faster beeping.
• Beeping rate varies continuously: objects within close range produce rapid beeps, while distant objects produce slower beeps.
• Code written in Arduino IDE, providing intuitive distance awareness through audio cadence alone.

Feedback & Audio Output

• Dual feedback system: Raspberry Pi's text-to-speech (pyttsx3) module announces detected object types, while Arduino controls beeping for distance awareness.
• Arduino beeping provides continuous, non-verbal distance feedback—allowing users to intuitively gauge proximity by beep frequency.
• Example event: Pi announces "Chair ahead" via speaker while Arduino beeps rapidly if the chair is close.

3D Design & Form Factor

• 3D-printed lightweight casing for camera, ultrasonic sensor, and battery pack.
• Designed for chest-mount or handheld operation with minimal wiring.
• Entire prototype assembled from readily available parts under $75 USD.

Results

• Real-time object detection and distance awareness on embedded hardware with dual feedback system.
• Achieved stable YOLOv3 inference at ~10 FPS on Raspberry Pi and responsive Arduino beeping alerts.
• Dual audio guidance: spoken object identification from Pi and distance-based beeping frequency from Arduino, providing comprehensive obstacle awareness up to 5 m away.
• Total system cost: ≈$72, compared to $300–$600 for commercial alternatives (back in 2022/23).
• Demonstrated a functional, human-centered assistive device merging AI perception and physical sensing.

Challenges & Insights

• Compute limitations: optimizing YOLOv3 inference on the Pi required input resizing and selective layer loading.
• Power efficiency: balanced 5V and 3.3V rails to run both boards safely from a single battery pack.
• Hardware durability: early 3D-printed mounts cracked—resolved using reinforced PLA and rubber isolation pads.
• Learned that splitting compute tasks (vision vs sensing) greatly improves performance and stability on low-cost hardware.

Future Improvements

• Upgrade to YOLOv5-Nano or YOLOv8-Lite for higher FPS and lower power draw.
• Add stair/elevation detection via a downward-facing depth or ToF sensor.
• Implement vibration motors for silent haptic feedback.
• Enhance enclosure aesthetics and weatherproofing for outdoor use.
• Deploy on Jetson Nano or Pi 5 for advanced edge AI applications.

Key Takeaways

• Built a fully functional assistive vision system integrating YOLOv3 AI and Arduino sensing for < $75.
• Demonstrated practical expertise in edge AI, sensor fusion, and real-time embedded programming.
• Proved that affordable, open-source solutions can deliver meaningful accessibility technology.

Overview

This project demonstrates the design and implementation of a digital circuit for Pulse Width Modulation (PWM) control of a robotic arm using the DE1-SoC development board. The system allows users to manipulate servo motor positions in real time through push buttons and switches, with live angular feedback displayed on HEX outputs. The work bridges embedded systems theory and hardware-level control in robotics.

Objective

Develop a user-configurable embedded system that:

• Generates PWM signals to control servo motor positions (0°–180°).
• Provides intuitive manual control via push buttons and switches.
• Displays servo position feedback on HEX displays.
• Supports multi-servo coordination with enable toggles for each joint.

Tools & Technologies

Hardware: DE1-SoC Board, 5-Servo Robotic Arm

Software: Intel Quartus Prime

Design Components: Counters, Comparators, Adders, Multipliers, PWM Signal Generators

Programming Concepts: Embedded logic, digital circuit design, duty cycle conversion

Process

PWM Circuit Design

• Developed a mathematical relationship to convert servo angles (0°–180°) into appropriate PWM duty cycle values.
• Implemented the conversion logic in Quartus Prime using multiplication and addition blocks.
• Compared the calculated duty cycle with an up counter to generate PWM output corresponding to servo position.

User Interface Integration

• Added push buttons to increase/decrease servo angles and switches to change direction.
• Implemented enable logic so users could toggle servo control individually.
• Real-time position data displayed on HEX output as degrees.

Multi-Servo Expansion

• Extended control logic to all five servos.
• Each servo had an independent enable switch, allowing simultaneous or isolated movement.
• System tested for coordinated arm movement across full range of motion.

Results

• Achieved smooth, real-time servo control through PWM signal generation.
• Fully functional robotic arm capable of precise angular adjustments and multi-servo coordination.
• Validated theoretical PWM models through practical implementation.
• Demonstrated the scalability of embedded digital control systems for robotic applications.

Challenges & Insights

• Hardware constraints (e.g., I/O bandwidth and servo lag) affected precision slightly.
• Learned how digital logic limitations translate into real-world mechanical performance.
• Reinforced the value of iterative calibration between hardware and control software.

Future Improvements

• Integrate closed-loop feedback using servo encoders for higher accuracy.
• Incorporate sensor inputs (e.g., object detection, position sensors) for semi-autonomous control.
• Migrate design to FPGA-based real-time control for lower latency and higher precision.

Key Takeaways

• Demonstrated mastery of PWM signal design and servo control.
• Combined digital logic design, embedded systems, and robotics mechanics in one functional prototype.
• Built a scalable foundation for autonomous robotic control systems.

Overview

A real-time motion sensing system that demonstrates how FPGA hardware and embedded software can work together to create responsive orientation tracking. By bridging an accelerometer sensor with custom FPGA logic and C++ processing, the system instantly converts physical tilt into live visual feedback—showcasing the foundation of how robots, drones, and smart devices understand their position in space.

Objective

Build a system that reads motion sensor data at the hardware level, processes it in real time, and displays orientation angles instantly—demonstrating the core principles behind how autonomous systems perceive and respond to their environment.

Tools & Technologies

Hardware: DE1-SoC FPGA Board, ADXL345 Accelerometer

Software: Quartus Prime, C++, SystemVerilog

Techniques: I²C sensor communication, Memory-mapped I/O, Hardware-software co-design

How It Works

The system operates on two levels working in perfect sync:

Hardware Layer (FPGA): Custom digital logic reads raw acceleration data from the onboard ADXL345 sensor using I²C communication. The FPGA instantly processes this data—converting acceleration values into meaningful tilt angles (0°–180°) using optimized arithmetic circuits—and displays the result on HEX displays.

Software Layer (Embedded C++): A modular C++ application running on the processor handles sensor initialization, memory-mapped register access, and real-time data streaming to a terminal interface. The software and hardware communicate through shared memory, creating seamless coordination between low-level circuits and high-level processing.

The Result: Physical tilt translates to instant visual feedback with sub-50ms latency—demonstrating the power of hardware-software co-design for creating responsive embedded systems.

Results

• Real-time orientation tracking with ±2° accuracy and sub-50ms response time
• Seamless synchronization between FPGA hardware and embedded software layers
• Reliable continuous operation with stable sensor readings and visual feedback
• Demonstrated foundation for motion control in robotics, stabilization systems, and navigation

Challenges & Insights

• Synchronizing hardware timing with software processing required careful attention to I²C protocols and memory-mapped register access
• Learned how splitting tasks between FPGA and processor creates more efficient, responsive embedded systems
• Gained hands-on experience bridging the gap between low-level hardware design and high-level software engineering

Future Enhancements

• Expand to full 3D orientation tracking with sensor fusion and Kalman filtering for drone stabilization
• Add gesture recognition capabilities for intuitive human-robot interaction
• Implement wireless data streaming for remote monitoring and control
• Integrate with machine learning for predictive motion analysis and anomaly detection

Key Takeaways

• Built a complete hardware-software sensing system showcasing how autonomous devices perceive orientation and motion
• Mastered the art of co-design—combining FPGA hardware acceleration with embedded C++ for optimal performance
• Demonstrated practical skills applicable to robotics, drones, wearables, and any system requiring real-time motion sensing

Overview

This project explores the design, acquisition, and digital processing of electrocardiogram (ECG) signals using both analog circuitry and digital filtering techniques. The work builds a complete signal chain — from biopotential amplification and noise filtering to automated heart-rate extraction through MATLAB-based digital signal processing.

Objective

Design and implement a complete ECG acquisition and analysis system that:

• Accurately captures ECG signals from human bio-potentials.
• Amplifies and filters signals using instrumentation amplifiers and analog filters.
• Digitizes, cleans, and processes signals via digital filters (Butterworth and Parks-McClellan).
• Automates heart-rate detection and visualization.

Tools & Technologies

Hardware: AD627 Instrumentation Amplifier, LT1490 Op-Amp, DAQ Device, Electrodes

Software: MATLAB, Simulink, NI Multisim

Techniques: Analog & Digital Filter Design (High-Pass, Low-Pass, Notch), Butterworth and Parks-McClellan Filters, Frequency Response Analysis, Heartbeat Peak Detection and BPM Automation, Signal Visualization and FFT Analysis

Process

Instrumentation Amplifier Design

• Designed an AD627-based instrumentation amplifier for bio-potential signal capture.
• Achieved appropriate gain for physiological signal levels with verified cutoff frequencies.
• Tested common-mode rejection at 60 Hz, confirming strong noise suppression.
• Used dual battery isolation for safety during human connection.
• Established a stable foundation for biomedical data collection.

Analog Signal Conditioning

• Enhanced the circuit with high-pass and low-pass filters to remove DC drift and high-frequency noise.
• Designed high-pass filter with ultra-low cutoff frequency to preserve baseline stability.
• Implemented tunable low-pass filter to optimize signal clarity.
• Evaluated the effects of different cutoff frequencies on waveform clarity, finding optimal balance between noise reduction and signal fidelity.
• Captured live ECG signals with variable heart rates under exertion, observing expected physiological response.
• Output data recorded via DAQ and visualized in MATLAB.

Digital Filtering and Heart-Rate Automation

• Imported recorded ECG signals into MATLAB for digital processing.
• Designed low-pass Butterworth filter with appropriate passband and stopband characteristics.
• Implemented notch filter to remove 60 Hz power-line interference.
• Compared multiple cutoff frequencies and observed their impact on the QRS complex.
• Developed Parks-McClellan filter for sharper cutoff characteristics.
• Applied automated peak detection and calculated heart rate across multiple recordings.
• Integrated FFT analysis to evaluate frequency distribution and confirm effective noise removal.

Results

• Produced a fully functional ECG signal chain, capable of real-time acquisition, filtering, and heart-rate computation.
• Achieved clean, high-fidelity ECG waveforms suitable for diagnostic interpretation.
• Validated theoretical design through experimental data and simulation.
• Demonstrated the effectiveness of combined analog-digital signal processing in biomedical instrumentation.

Challenges & Insights

• Managing the trade-off between filter strength and waveform integrity required iterative tuning.
• Learned how component tolerances affect real-world filter behavior.
• Highlighted the necessity of isolating patient circuits and optimizing DAQ dynamic range.
• Reinforced understanding of how signal conditioning decisions directly impact diagnostic accuracy.

Future Improvements

• Implement a closed-loop adaptive filter to dynamically suppress noise in real time.
• Integrate microcontroller-based processing for portable ECG monitoring.
• Add machine-learning algorithms to classify arrhythmias from extracted features.

Key Takeaways

• Built an end-to-end biomedical signal processing pipeline.
• Strengthened skills in both hardware circuit design and digital signal processing.
• Demonstrated the practical application of EE and biomedical engineering principles to healthcare technology.

Overview

This project focused on developing a machine learning–based demand forecasting system for retail stores operating across multiple distribution channels. The model predicts monthly product demand by learning from five years of historical sales data, helping stores optimize inventory management, reduce overstock and shortage costs, and improve overall operational efficiency. Using a combination of Linear Regression, Random Forest, and XGBoost, the study compared model performance to determine which algorithm produced the most accurate and generalizable forecasts for store-level sales prediction.

Objective

To build and compare machine learning models that:

• Predict store-level item demand for 30-day periods based on historical sales.
• Automate inventory and logistics planning for multi-channel retail systems.
• Identify the most effective forecasting model among Linear Regression, Random Forest, and XGBoost.
• Reduce forecasting error metrics (RMSE, MAE) while maintaining model interpretability.

Tools & Technologies

Languages: Python

Libraries: NumPy, Pandas, scikit-learn, XGBoost, Matplotlib

Techniques: Feature Engineering, Time-Series Regression, Ensemble Learning, Data Cleaning, Cross-Validation

Algorithms: Linear Regression (Baseline), Random Forest (Ensemble Bagging), XGBoost (Gradient Boosting)

Evaluation Metrics: RMSE, MAE, R²

Process

Data Collection and Preparation

• Aggregated five years of sales data from multiple retail branches.
• Performed data integration, cleaning, and transformation — converting raw records into daily and monthly sales formats.
• Standardized date formats, encoded categorical data (store and item IDs), and removed outliers and duplicate entries.
• Conducted feature engineering, including: Lag features for previous month sales, Moving averages (MA) and Exponentially Weighted Moving Averages (EWMA) to capture temporal trends, Date-based features (month, quarter, year, weekday) to identify seasonality.

Model Development

• Split data into training, validation, and test sets to ensure unbiased evaluation.
• Framed the time series problem as a regression task, transforming each store-item pair into a sequence of historical predictors.
• Models trained: Linear Regression (Provided a high-bias baseline, fast to train, interpretable, and performed strongly on stationary datasets), Random Forest (Handled nonlinear relationships and variance through bagging; reduced overfitting by aggregating many trees), XGBoost (Implemented gradient boosting with regularization for efficient handling of residual errors and sparse data).

Model Training and Evaluation

• Tuned hyperparameters for ensemble models: n_estimators, max_depth, learning_rate, min_child_weight, subsample, and colsample_bytree (for XGBoost), max_features, min_samples_split, and bootstrap (for Random Forest).
• Evaluated models using unseen 2017 test data, showing Linear Regression achieved the lowest RMSE and MAE, outperforming ensemble models despite their higher complexity.
• Results demonstrated that the data's relationships were primarily linear and well-behaved.

Results

• Achieved high predictive accuracy across all models, with R² > 0.97 for each.
• Linear Regression provided the most stable and interpretable performance, making it ideal for smaller retailers seeking transparent forecasting logic.
• Random Forest delivered robust performance on noisy data, and XGBoost showed strong adaptability with larger datasets.
• The comparison highlighted that feature engineering and data quality were more influential than model complexity in forecasting accuracy.

Challenges & Insights

• Handling large datasets required memory-efficient feature generation and data reduction.
• Ensuring consistent date alignment and normalization across multiple branches was crucial for valid predictions.
• The project demonstrated that simpler models often outperform complex ones when feature space is well-defined and regularized.
• Learned the importance of cross-validation and hyperparameter tuning in balancing bias–variance tradeoffs.

Future Improvements

• Implement LightGBM and LSTM recurrent neural networks for deep time-series forecasting.
• Integrate real-time inventory data feeds for adaptive retraining.
• Add economic indicators (holidays, promotions, regional events) to improve model context.
• Deploy as a web-based forecasting dashboard for end-user access and visualization.

Key Takeaways

• Developed a complete machine learning pipeline for multichannel retail demand forecasting.
• Demonstrated proficiency in feature engineering, regression modeling, and ensemble learning.
• Highlighted the importance of model interpretability in real-world inventory systems.
• Gained practical experience in transforming raw business data into operational decision intelligence.

Overview

A deep dive into the transistors that make modern computing possible. MOSFETs are the fundamental building blocks of every processor, memory chip, and digital device—billions of them working together to perform computations at lightning speed. This project explores how these tiny switches operate, how they're optimized for ultra-low power consumption, and how they're combined to create logic gates that form the foundation of all digital systems.

Objective

Understand how transistors switch and amplify signals at the device level, then apply that knowledge to design energy-efficient logic circuits—revealing why CMOS technology powers virtually every modern electronic device.

Tools & Technologies

Hardware: MOSFET transistors (nMOS & pMOS), oscilloscope, function generator, power supply

Software: LTspice circuit simulation

Techniques: Transistor characterization, CMOS logic design, low-power circuit optimization

What I Built

Single-Transistor Inverter: Started with the simplest digital circuit—a transistor that inverts signals (1→0, 0→1). By measuring how it responds to different voltages, I extracted the fundamental parameters that define transistor behavior and discovered how it can both amplify analog signals and perform digital switching.

CMOS Inverter: Upgraded to CMOS (Complementary MOS) design by pairing nMOS and pMOS transistors. The result? A circuit that consumes just 0.1 mW—dramatically more efficient than the resistive version. This revealed why CMOS became the dominant technology: it only uses power when switching, not when idle, enabling billions of transistors on a single chip without melting.

Custom Logic Gate: Designed a 3-input OR gate from scratch using complementary transistor pairs. By understanding how transistors connect in series and parallel, I built a functional logic element—the same approach used to create the complex circuits inside modern processors.

Results

• Successfully characterized transistor behavior from device physics to digital logic
• Achieved ultra-low-power CMOS circuits consuming only 0.1 mW
• Built functional logic gates from fundamental transistor principles
• Gained hands-on understanding of why CMOS dominates modern electronics

Challenges & Insights

• Discovered why precise biasing matters—small voltage changes dramatically affect transistor behavior
• Learned why CMOS revolutionized computing: it only consumes power during switching, enabling modern chips with billions of transistors
• Gained appreciation for the elegance of complementary design—using both n-type and p-type transistors together

Future Enhancements

• Design more complex logic circuits: adders, multiplexers, and sequential elements
• Explore nanoscale effects in modern transistors as feature sizes shrink below 10nm
• Simulate chip-scale layouts to understand how billions of transistors interconnect
• Investigate emerging technologies like FinFETs and gate-all-around transistors

Key Takeaways

• Understood transistor-level fundamentals that power every digital device
• Discovered why CMOS technology enables modern computing at scale
• Built working circuits from basic principles—the same approach Intel, AMD, and Apple use for their chips
• Gained foundation for VLSI design, processor architecture, and low-power electronics